The design process for complex modern integrated circuits (ICs) involves many different steps to help manage the complexity and produce an IC that functions as intended. ICs can contain many millions, or even billons of transistors and other electronic structures such as resistors, capacitors, diodes, and interconnecting conductors; therefore, managing the complexity of the ICs is crucial to creating electronic designs that operate as planned. One of the steps in the design process of an IC is the physical verification process, which is typically highly automated. The physical verification process for an integrated circuit (IC) is a design step taken by semiconductor manufacturers before commencing the fabrication of an IC. In order to be able to check a design, semiconductor foundries first define a set of design rules for manufacturing (DRM) for IC designers, which, when followed, ensure successful manufacture and high yield of a design during the fabrication process. The DRM provide a benchmark against which the design can be tested. The DRM are defined as a set of geometric relationships between manufacturing layers, layers which in turn are used to create an IC. A physical design layout can include hundreds of layers used during the fabrication process to create transistors and electrical interconnect in the IC. The semiconductor process has grown in complexity and a physical design layout has to adhere to thousands of design rules before a design can be successfully fabricated. Use of a design rule checking (DRC) physical verification tool is an industry standard process for implementing the semiconductor's DRM.
The DRM can define many different parameters—such as width, spacing, angle, enclosure, density and electrical connectivity rules for design layers—which in turn are translated into a DRC runset. A DRC runset is defined as set of DRC operations that verify the required DRM rules. A DRC tool provides a set of operations, or commands, from which a designer selects and combines to form sequence of DRC commands to satisfy each DRM rule. The complexity of modern DRM rules means that a DRC runset with 20,000 or more DRC commands is often required to verify technology nodes smaller than 28 nanometers (nm). Modern DRC physical verification tools have a large suite of geometric and electrical commands to effectively implement the complex DRM rules. Many of these geometric and electrical commands result in the implementation of a unique algorithm that is not shared between individual commands, thus resulting in a very complex DRC tool with many algorithms selected.
Large ICs are typically built using a hierarchical method that begins with the creation of small child cells which are in turn combined into larger parent cells, which are then successively used to build larger and larger cells to create an IC hierarchical design. The hierarchal nature of the design allows physical verification tools to selectively access portions of the design in an efficient manner, a necessity in processing cutting-edge, extremely large designs. Various forms of flattening processes present an alternative to hierarchical processing, but the flattening processes can result in very large increases in processing time and are often not feasible for design verification.